1. Field of the Invention
This invention relates generally to voltage driver circuits and, in particular, to an improved voltage driver circuit for driving n-channel MOS RAMs in a data processing system.
2. Description of the Prior Art
In recent years, data processing systems have been evolving towards more efficient and more compact units. This trend has been paralleled by the development of systems which operate at ever-increasing speeds. Typifying these trends is the development and success of mini-computers.
An essential component of a data processing system is the memory unit. Random access memories (RAMs) have recently evolved from p-channel devices to n-channel metal-oxide semiconductor field effect transistors (MOSFETs). This development has numerous advantages. Where the typical p-channel device, such as an Intel 1103, would contain 1,024 (or approximately 1K) memory locations per bit, an n-channel MOSFET, such as a TMS 4030, contains 4,096 (or approximately 4K) memory locations per bit. In addition, the n-channel device is capable of operating at faster speeds. Both the increased density and speed of the n-channel devices make them clearly more desirable for modern data processing and mini-computer usage. Unfortunately, the development of improved RAMs has significantly preceded the development of appropriate driver circuits for operating these RAMs.
P-channel RAMs typically require operation in a memory system environment which has available three positive power supplies or three system levels of power (5V, 12V and 15-20V). N-channel systems typically have only two positive power supplies available (5V and 12V and a third supply at -3V to -5V). In addition, n-channel RAMs are particularly sensitive to input voltage levels and rise times of clock signals coupled to the chip enable input terminals.
Commonly used for driving the RAMs is a standard off-the-shelf quad TTL to MOS clock driver circuit. (Such a circuit is commonly produced by integrated circuit manufacturers, such as the SN75365 by Texas Instruments.) However, the circuit was originally designed for driving p-channel memory devices. Its use in an n-channel environment presents several difficulties. If only the two commonly available (5 volt and 12 volt) system-level power supplies are used, the peak voltage level and rise time parameters will be unacceptable for properly driving n-channel RAMs. Prior art remedies to this deficiency required supplying a third high-level voltage (greater than 12 volts) to the driver circuit. This, however, is a costly solution, in terms of dollars as well as in space and weight.
Another method of remedying this problem is to increase the high level (12 volt) system voltage presently available in the RAM environment. The increased voltage may then be stepped down to 12 volts, thereby effectively providing three voltage levels for use by the driver circuit. However, increasing the voltage necessitates both alteration of the system as well as increased power requirements.